M3 Architecture Research Group
Computer Systems Laboratory
361 Frank H.T. Rhodes Hall
Ithaca, NY 14853 USA
m3 at csl.cornell.edu
Welcome to the Microprocessor, Multicore, and Multiprocessor architecture research group. Our research seeks to define the architectures that will shape the future of computing in our society. Our goal is to improve the performance, programmability, reliability, and energy efficiency of next-generation computers.
We are part of Cornell's Computer Systems Laboratory.
M3 Research Interests
- Checkpointed processor architectures
- Power-aware parallel architectures
- Reconfigurable and self-optimizing hardware
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M3 People
Faculty
José F. Martínez
Associate Professor, ECE
Graduate Field Member, ECE and CS
Ph.D. '02, UIUC
MS/Ph.D. Students
Ramazan Bitirgen
McMullen Fellowship, 2005-06
Saugata Ghose
NDSEG Fellowship, 2008-11
Cornell Fellowship, 2007-08
Meyrem Kırman
Intel Fellowship, 2006-08
McMullen Fellowship, 2003-04
Nevin Kırman
IBM Scholarship, 2008-09
Intel Fellowship, 2005-07
Janani Mukundan
MS/Ph.D. Graduates
Engin İpek, Ph.D. '08 (1st employment: Microsoft Research)
Jian Li, Ph.D. '06 (1st employment: IBM Research)
Undergraduate Students
Jiho "Ray" Choi, BS '08 (became grad student, Cornell)
Hyun Goo Kang, BS '08 (joined Google)
Kon-Hyong "Kenny" Kim, BS '08 (became grad student, Cornell)
Cherie Kwan, BS '08 (joined Microsoft)
Noah Sturcken, BS '08 (became grad student, Columbia)
Andrew Tibbits, BS '07 (became grad student, Stanford)
Carole-Jean Wu, BS '06 (became grad student, Princeton)
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M3 Fully Refereed Archival Publications [BiBTeX]
ISCA 2008
E. İpek, O. Mutlu, J.F. Martínez, and R. Caruana. Self-optimizing memory controllers: A reinforcement learning approach. In Intl. Symp. on Computer Architecture, Beijing, China, June 2008 [PDF]
MICRO 2007
A. Basu, N. Kırman, M. Kırman, M. Chaudhuri, and J.F. Martínez. Scavenger: A new last level cache architecture with global block priority. In Intl. Symp. on Microa rchitecture, Chicago, IL, Dec. 2007 [PDF]
DSN 2007
C.C. LaFrieda, E. İpek, J.F. Martínez, and R. Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. In Intl. Conf. on Dependable systems and Networks, Edinburgh, Scotland, June 2007 [PDF]
ISCA 2007
E. İpek, M. Kırman, N. Kırman, and J.F. Martínez. Core Fusion: Accommodating software diversity in chip multiprocessors. In Intl. Symp. on Computer Architecture, San Diego, CA, June 2007 [PDF]
Earlier version appears in Workshop on Complexity-effective Design, conc. with ISCA, Boston, MA, June 2006
IEEE Micro 2007 TOP PICKS
N. Kırman, M. Kırman, R.K. Dokania, J.F. Martínez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in bus-based multicore design. In IEEE Micro Top Picks from Computer Architecture Conferences, Jan.-Feb. 2007 [PDF]
MICRO 2006 BEST PAPER NOMINATION
N. Kırman, M. Kırman, R.K. Dokania, J.F. Martínez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors. In Intl. Symp. on Microachitecture, Orlando, FL, Dec. 2006 [PDF]
HPCA 2006
J. Li and J.F. Martínez. Dynamic power-performance adaptation of parallel computation on chip multlprocessors. In Intl. Symp. on High-Performance Computer Architecture, Austin, TX, Feb. 2006 [PDF]
ACM TACO 2005
J. Li and J.F. Martínez. Power-performance considerations of parallel computing on chip multlprocessors. In ACM Trans. on Architecture and Code Optimization, Vol. 2, No. 4, Dec. 2005 [PDF]
MICRO 2005
M. Kırman, N. Kırman, and J.F. Martínez. Cherry-MP: Correctly integrating checkpointed early resource recycling in chip multiprocessors. In Intl. Symp. on Microachitecture, Barcelona, Spain, Nov. 2005 [PDF]
ISPASS 2005
J. Li and J.F. Martínez. Power-performance implications of thread-level parallelism in chip multiprocessors. In Intl. Symp. on Performance Analysis of Systems and Software, Austin, TX, Mar. 2005 [PDF]
Earlier version appears in IBM Watson Conf. on Power and Performance Issues of Architectures, Circuits, and Compilers, Yorktown Heights, NY, Oct. 2004
HPCA 2005 BEST PAPER AWARD
N. Kırman, M. Kırman, M. Chaudhuri, and J.F. Martínez. Checkpointed early load retirement. In Intl. Symp. on High-Performance Computer Architecture, San Francisco, CA, Feb. 2005 (opening session) [PDF]
Earlier version appears in Workshop on Value Prediction and Value-based Optimization, conc. with ASPLOS, Boston, MA, Oct. 2004
ACM TACO 2004
A. Cristal, O. Santana, M. Valero, and J.F. Martínez. Toward kilo-instruction processors. In ACM Trans. on Architecture and Code Optimization, Vol. 1, No. 4, Dec. 2004 [PDF]
HPCA 2004
J. Li, J.F. Martínez, and M.C. Huang. The thrifty barrier: Energy-aware synchronization in shared-memory multiprocessors. In Intl. Symp. on High-Performance Computer Architecture, Madrid, Spain, Feb. 2004 (opening session) [PDF]
IEEE Micro 2003 TOP PICKS
J.F. Martínez and J. Torrellas. Speculative synchronization: Programmability and performance for parallel codes. In IEEE Micro Top Picks from Microarchitecture Conferences, Nov.-Dec. 2003 [PDF]
IEEE Computer Architecture Letters 2003
A. Cristal, J.F. Martínez, J. Llosa, and M. Valero. A case for resource-conscious out-of-order processors. In IEEE Computer Architecture Letters, Vol. 2, Oct. 2003 [PDF]
MICRO 2002
J.F. Martínez, J. Renau, M.C. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed early resource recycling in out-of-order microprocessors. In Intl. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 2002 (opening session) [PDF]
M3 Publications (Other)
J.F. Martínez, Editor. Architectures and Systems for Cognitive Processing: Summary of Recommendations. Cornell-AFRL Workshop on Research Directions on Architectures and Systems for Cognitive Processing, Ithaca, NY, July 2005
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