Publications

HPCA 17 - SWAP: Effective fine-grain management of shared last-level caches with minimum hardware support

X. Wang, S. Chen, J. Setter, and J.F. Martínez. SWAP: Effective fine-grain management of shared last-level caches with minimum hardware support. In Intl. Symp. on High Performance Computer Architecture (HPCA), Austin, TX, Feb. 2017

[PDF]
@inproceedings{m3:hpca17,
  author = "Xiaodong Wang and Shuang Chen and Jeff Setter and Jos{'e} F. Mart{'i}nez",
  title = "SWAP: Effective fine-grain management of shared last-level caches with minimum hardware support",
  booktitle = "International Symposium on High-Performance Computer Architecture (HPCA)",
  address = "Austin, TX",
  month = feb,
  year = "2017" }
ASPLOS 16 - ReBudget: Trading off efficiency vs. fairness in market-based multicore resource allocation via runtime budget reassignment

X. Wang and J.F. Martínez. ReBudget: Trading off efficiency vs. fairness in market-based multicore resource allocation via runtime budget reassignment. In Intl. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, Apr. 2016

[PDF]
@inproceedings{m3:asplos16,
  author = "Xiaodong Wang and Jos{'e} F. Mart{'i}nez",
  title = "{ReBudget}: Trading off efficiency vs. fairness in market-based multicore resource allocation via runtime budget reassignment",
  booktitle = "International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)",
  address = "Atlanta, GA",
  month = apr,
  year = "2016" }
FPL 15 - A fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference

S. Hurkat, J. Choi, E. Nurvitadhi, J.F. Martínez, and R. Rutenbar. A fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. In Intl. Conf. on Field-Programmable Logic (FPL), London, England, Sep. 2015

[PDF]
@inproceedings{m3:fpl15,
  author = "Skand Hurkat and Jungwook Choi and Eriko Nurvitadhi and Jos{'e} F. Mart{'i}nez and Rob Rutenbar",
  title = "A fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference",
  booktitle = "International Conference on Field Programmable Logic (FPL)",
  address = "London, England",
  month = sep,
  year = "2015" }
HPCA 15 - XChange: A market-based approach to scalable dynamic multi-Resource allocation in multicore architectures

X. Wang and J.F. Martínez. XChange: A market-based approach to scalable dynamic multi-Resource allocation in multicore architectures. In Intl. Symp. on High Performance Computer Architecture (HPCA), San Francisco, CA, Feb. 2015

Nominated for Best Paper Award

[PDF]
@inproceedings{m3:hpca15,
  author = "Xiaodong Wang and Jos{'e} F. Mart{'i}nez",
  title = "{XChange}: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures",
  booktitle = "International Symposium on High-Performance Computer Architecture (HPCA)",
  address = "San Francisco, CA",
  month = feb,
  year = "2015" }
FCCM 14 - GraphGen: An FPGA framework for vertex-centric graph computation

E. Nurvitadhi, G. Weisz, Y. Wang, S. Hurkat, M. Nguyen, J.C. Hoe, J.F. Martínez, and C. Guestrin. GraphGen: An FPGA framework for vertex-centric graph computation. In Intl. Conf. on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014

[PDF]
@inproceedings{m3:fccm14,
  author = "Eriko Nurvitadhi and Gabriel Weisz and Yu Wang and Skand Hurkat and Marie Nguyen and James C. Hoe and Jos{\'e} F. Mart{\'\i}nez and Carlos Guestrin",
  title = "Graph{G}en: An {FPGA} framework for vertex-centric graph computation},
  booktitle = " International Conference on Field-Programmable Custom Computing Machines (FCCM)",
  address = "Boston, MA",
  month = may,
  year = "2014" }
ISCA 13 - Improving Memory Scheduling via Processor-Side Load Criticality Information

S. Ghose, H. Lee, and J.F. Martínez. Improving Memory Scheduling via Processor-Side Load Criticality Information. In Intl. Symp. on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013

[PDF]
@inproceedings{m3:isca13:ghose,
  author = "Saugata Ghose and Hyodong Lee and Jos{\'e} F. Mart{\'\i}nez",
  title = "Improving memory scheduling via processor-side load criticality information",
  booktitle = "International Symposium on Computer Architecture (ISCA)",
  address = "Tel Aviv, Israel",
  month = june,
  year = "2013" }
ISCA 13 - Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems

J. Mukundan, H. Hunter, K.-H. Kim, J. Stuecheli, and J.F. Martínez. Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems. In Intl. Symp. on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013

[PDF]
@inproceedings{m3:isca13:mukundan,
  author = "Janani Mukundan and Hillery Hunter and Kyu-hyoun Kim and Jeff Stuecheli and Jos{\'e} F. Mart{\'\i}nez",
  title = "Understanding and mitigating refresh overheads in high-density {DDR4} {DRAM} systems",
  booktitle = "International Symposium on Computer Architecture (ISCA)",
  address = "Tel Aviv, Israel",
  month = june,
  year = "2013" }
ICS 12 - Overcoming single-thread performance hurdles in the Core Fusion reconfigurable multicore architecture

J. Mukundan, S. Ghose, R. Karmazin, E. İpek, and J.F. Martínez. Overcoming single-thread performance hurdles in the Core Fusion reconfigurable multicore architecture. In Intl. Symp. on Supercomputing (ICS), Venice, Italy, June 2012

[PDF]
@inproceedings{m3:ics12,
  author = "Janani Mukundan and Saugata Ghose and Robert Karmazin and Engin {\.I}pek and Jos{\'e} F. Mart{\'\i}nez",
  title = "Overcoming single-thread performance hurdles in the {C}ore {F}usion reconfigurable multicore architecture",
  booktitle = "International Conference on Supercomputing (ICS)",
  address = "Venice, Italy",
  month = june,
  year = "2012" }
HPCA 12 - Multi-objective reconfigurable self-optimizing memory scheduler

J. Mukundan and J.F. Martínez. MORSE: Multi-objective reconfigurable self-optimizing memory scheduler. In Intl. Symp. on High-Performance Computer Architecture, New Orleans, LA, Feb. 2012

(Early version appears in Workshop on Energy-Effective Design, conc. with ISCA, June 2011.)

[PDF]
@inproceedings{m3:hpca12,
  author = "Janani Mukundan and Jos{\'e} F. Mart{\'\i}nez",
  title = "{MORSE}: {M}ulti-objective reconfigurable self-optimizing memory scheduler",
  booktitle = "International Symposium on High-Performance Computer Architecture (HPCA)",
  address = "New Orleans, LA",
  month = feb,
  year = "2012" }
ASPLOS 10 - An efficient all-optical on-chip interconnect based on oblivious routing

N. Kırman and J.F. Martínez. An efficient all-optical on-chip interconnect based on oblivious routing. In Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, Pittsburgh, PA, March 2010

[PDF]
@inproceedings{m3:asplos10
  author = "Nevin K{\i}rman and Jos{\'e} F. Mart{\'\i}nez",
  title = "An efficient all-optical on-chip interconnect based on oblivious routing",
  booktitle = "International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)",
  address = "Pittsburgh, PA",
  month = mar,
  year = "2010" }
IEEE Micro 09 - Dynamic multicore resource management: A machine learning approach

J.F. Martínez and E. İpek. Dynamic multicore resource management: A machine learning approach. IEEE Micro, Vol. 29, No. 5, Sep.-Oct. 2009

@article{m3:ieeemicro09,
  author = "Jos{\'e} F. Mart{\'\i}nez and Engin {\.I}pek",
  title = "Dynamic Multicore Resource Management: A Machine Learning Approach",
  journal = "IEEE Micro",
  volume = 29,
  number = 5,
  month = sep#--#oct,
  year = "2009" }
MICRO 08 - Coordinated management of multiple resources in chip multiprocessors

R. Bitirgen, E. İpek, and J.F. Martínez. Coordinated management of multiple resources in chip multiprocessors: A machine learning approach. In Intl. Symp. on Microarchitecture, Lake Como, Italy, Nov. 2008

[PDF]
@inproceedings{m3:micro08
  author = "Ramazan Bitirgen and Engin {\.I}pek and Jos{\'e} F. Mart{\'\i}nez",
  title = "Coordinated Management of Multiple Resources in Chip Multiprocessors: A Machine Learning Approach",
  booktitle = "International Symposium on Microarchitecture (MICRO)",
  address = "Lake Como, Italy",
  month = nov,
  year = "2008" }
ISCA 08 - Self-optimizing memory controllers: A reinforcement learning approach

E. İpek, O. Mutlu, J.F. Martínez, and R. Caruana. Self-optimizing memory controllers: A reinforcement learning approach. In Intl. Symp. on Computer Architecture, Beijing, China, June 2008

[PDF]
@inproceedings{m3:isca08
  author = "Engin {\.I}pek and Onur Mutlu and Jos{\'e} F. Mart{\'\i}nez and Rich Caruana",
  title = "Self-optimizing Memory Controllers: A Reinforcement Learning Approach",
  booktitle = "International Symposium on Computer Architecture (ISCA)",
  address = "Beijing, China",
  month = jun,
  year = "2008" }
MICRO 07 - Scavenger: A new last level cache architecture with global block priority

A. Basu, N. Kırman, M. Kırman, M. Chaudhuri, and J.F. Martínez. Scavenger: A new last level cache architecture with global block priority. In Intl. Symp. on Microa rchitecture, Chicago, IL, Dec. 2007

[PDF]
@inproceedings{m3:micro07
  author = "Arkaprava Basu and Meyrem K{\i}rman and Nevin K{\i}rman and Mainak Chaudhuri and Jos{\'e} F. Mart{\'\i}nez",
  title = "Scavenger: A New Last Level Cache Architecture with Global Block Priority",
  booktitle = "International Symposium on Microarchitecture (MICRO)",
  address = "Chicago, IL",
  month = dec,
  year = "2007" }
DSN 07 - Utilizing dynamically coupled cores to form a resilient chip multiprocessor

C.C. LaFrieda, E. İpek, J.F. Martínez, and R. Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. In Intl. Conf. on Dependable systems and Networks, Edinburgh, Scotland, June 2007

[PDF]
@inproceedings{m3:dsn07
  author = "Christopher LaFrieda and Engin {\.I}pek and Jos{\'e} F. Mart{\'\i}nez and Rajit Manohar",
  title = "Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor",
  booktitle = "International Conference on Dependable Systems and Networks (DSN)",
  address = "Edinburgh, Scotland",
  month = jun,
  year = "2007" }
ISCA 07 - Core Fusion: Accommodating software diversity in chip multiprocessors

E. İpek, M. Kırman, N. Kırman, and J.F. Martínez. Core Fusion: Accommodating software diversity in chip multiprocessors. In Intl. Symp. on Computer Architecture, San Diego, CA, June 2007

Early version appears in Workshop on Complexity-effective Design, conc. with ISCA, Boston, MA, June 2006

[PDF]
@inproceedings{m3:isca07
  author = "Engin {\.I}pek and Meyrem K{\i}rman and Nevin K{\i}rman and Jos{\'e} F. Mart{\'\i}nez",
  title = "{C}ore {F}usion: Accommodating Software Diversity in Chip Multiprocessors",
  booktitle = "International Symposium on Computer Architecture (ISCA)",
  address = "San Diego, CA",
  month = jun,
  year = "2007" }
IEEE Micro Top Picks 07 - Leveraging optical technology in bus-based multicore design

N. Kırman, M. Kırman, R.K. Dokania, J.F. Martínez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in bus-based multicore design. In IEEE Micro Top Picks from Computer Architecture Conferences, Jan.-Feb. 2007

@article{m3:ieeemicro07,
  author = "Nevin K{\i}rman and Meyrem K{\i}rman and Rajeev K. Dokania and Jos{\'e} F. Mart{\'\i}nez and Alyssa B. Apsel and Matthew A. Watkins and David H. Albonesi",
  title = "The Impact of Optical Technology in Bus-based Multicore Chip Design",
  journal = "IEEE Micro Top Picks from Computer Architecture Conferences",
  month = jan#--#feb,
  year = "2007" }
MICRO 06 - Leveraging optical technology in future bus-based chip multiprocessors

N. Kırman, M. Kırman, R.K. Dokania, J.F. Martínez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors. In Intl. Symp. on Microachitecture, Orlando, FL, Dec. 2006

Nominated for Best Paper Award

[PDF]
@inproceedings{m3:micro06,
  author = "Nevin K{\i}rman and Meyrem K{\i}rman and Rajeev K. Dokania and Jos{\'e} F. Mart{\'\i}nez and Alyssa B. Apsel and Matthew A. Watkins and David H. Albonesi",
  title = "Leveraging Optical Technology in Future Bus-based Chip Multiprocessors",
  booktitle = "International Symposium on Microarchitecture (MICRO)",
  address = "Orlando, FL",
  month = dec,
  year = "2006" }
HPCA 06 - Dynamic power-performance adaptation of parallel computation on chip multlprocessors

J. Li and J.F. Martínez. Dynamic power-performance adaptation of parallel computation on chip multlprocessors. In Intl. Symp. on High-Performance Computer Architecture, Austin, TX, Feb. 2006

[PDF]
@inproceedings{m3:hpca06,
  author = "Jian Li and Jos{\'e} F. Mart{\'\i}nez",
  title = "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors",
  booktitle = "International Symposium on High-Performance Computer Architecture (HPCA)",
  address = "Austin, TX",
  month = feb,
  year = "2006" }
ACM TACO 05 - Power-performance considerations of parallel computing on chip multlprocessors

J. Li and J.F. Martínez. Power-performance considerations of parallel computing on chip multlprocessors. In ACM Trans. on Architecture and Code Optimization, Vol. 2, No. 4, Dec. 2005

@article{m3:taco05,
  author = "Jian Li and Jos{\'e} F. Mart{\'\i}nez",
  title = "Power-Performance Considerations of Parallel Computing on Chip Multiprocessors",
  journal = "ACM Transactions on Architecture and Code Optimization (TACO)",
  volume = 2,
  number = 4,
  pages = "397--422"
  month = dec,
  year = "2005" }
MICRO 05 - Cherry-MP: Correctly integrating checkpointed early resource recycling in chip multiprocessors

M. Kırman, N. Kırman, and J.F. Martínez. Cherry-MP: Correctly integrating checkpointed early resource recycling in chip multiprocessors. In Intl. Symp. on Microachitecture, Barcelona, Spain, Nov. 2005

[PDF]
@inproceedings{m3:micro05,
  author = "Meyrem K{\i}rman and Nevin K{\i}rman and Jos{\'e} F. Mart{\'\i}nez",
  title = "Cherry-{MP}: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors",
  booktitle = "International Symposium on Microarchitecture (MICRO)",
  address = "Barcelona, Spain",
  month = nov,
  year = "2005" }
ISPASS 05 - Power-performance implications of thread-level parallelism in chip multiprocessors

J. Li and J.F. Martínez. Power-performance implications of thread-level parallelism in chip multiprocessors. In Intl. Symp. on Performance Analysis of Systems and Software, Austin, TX, Mar. 2005

Early version appears in IBM Watson Conf. on Power and Performance Issues of Architectures, Circuits, and Compilers, Yorktown Heights, NY, Oct. 2004

[PDF]
@inproceedings{m3:ispass05,
  author = "Jian Li and Jos{\'e} F. Mart{\'\i}nez",
  title = "Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors",
  booktitle = "International Symposium on Performance Analysis of Systems and Software (ISPASS)",
  address = "Austin, TX",
  month = mar,
  year = "2005" }
HPCA 05 - Checkpointed early load retirement

N. Kırman, M. Kırman, M. Chaudhuri, and J.F. Martínez. Checkpointed early load retirement. In Intl. Symp. on High-Performance Computer Architecture, San Francisco, CA, Feb. 2005

Early version appears in Workshop on Value Prediction and Value-based Optimization, conc. with ASPLOS, Boston, MA, Oct. 2004

[PDF]
@inproceedings{m3:hpca05,
  author = "Nevin K{\i}rman and Meyrem K{\i}rman and Mainak Chaudhuri and Jos{\'e} F. Mart{\'\i}nez",
  title = "Checkpointed Early Load Retirement",
  booktitle = "International Symposium on High-Performance Computer Architecture (HPCA)",
  address = "San Francisco, CA",
  month = feb,
  year = "2005" }
ACM TACO 04 - Toward kilo-instruction processors

A. Cristal, O. Santana, M. Valero, and J.F. Martínez. Toward kilo-instruction processors. In ACM Trans. on Architecture and Code Optimization, Vol. 1, No. 4, Dec. 2004

[PDF]
@article{m3:taco04,
  author = "Adri{\'a}n Cristal and Oliverio J. Santana and Mateo Valero and Jos{\'e} F. Mart{\'\i}nez",
  title = "Toward {K}ilo-Instruction Processors",
  journal = "ACM Transactions on Architecture and Code Optimization (TACO)",
  volume = 1,
  number = 4,
  pages = "389--417",
  month = dec,
  year = "2004" }
HPCA 04 - The thrifty barrier: Energy-aware synchronization in shared-memory multiprocessors

J. Li, J.F. Martínez, and M.C. Huang. The thrifty barrier: Energy-aware synchronization in shared-memory multiprocessors. In Intl. Symp. on High-Performance Computer Architecture, Madrid, Spain, Feb. 2004 (opening session)

[PDF]
@inproceedings{m3:hpca04,
  author = "Jian Li and Jos{\'e} F. Mart{\'\i}nez and Michael C. Huang",
  title = "The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors",
  booktitle = "International Symposium on High-Performance Computer Architecture (HPCA)",
  address = "Madrid, Spain",
  month = feb,
  year = "2004" }
IEEE Micro Top Picks 03 - Speculative synchronization: Programmability and performance for parallel codes

J.F. Martínez and J. Torrellas. Speculative synchronization: Programmability and performance for parallel codes. In IEEE Micro Top Picks from Microarchitecture Conferences, Nov.-Dec. 2003

[PDF]
@article{m3:ieeemicro03,
  author = "Jos{\'e} F. Mart{\'\i}nez and Josep Torrellas",
  title = "Speculative Synchronization: Programmability and Performance in Parallel Codes",
  journal = "IEEE Micro Top Picks form Microarchitecture Conferences",
  month = nov#--#dec,
  year = "2003" }
IEEE CAL - A case for resource-conscious out-of-order processors

A. Cristal, J.F. Martínez, J. Llosa, and M. Valero. A case for resource-conscious out-of-order processors. In IEEE Computer Architecture Letters, Vol. 2, Oct. 2003

[PDF]
@article{m3:ieeecal03,
  author = "Adri{\'a}n Cristal and Jos{\'e} F. Mart{\'\i}nez and Josep Llosa and Mateo Valero",
  title = "A Case for Resource-conscious Out-of-order Processors",
  journal = "IEEE TCCA Computer Architecture Letters",
  volume = 2,
  month = oct,
  year = "2003" }
MICRO 02 - Cherry: Checkpointed early resource recycling in out-of-order microprocessors

J.F. Martínez, J. Renau, M.C. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed early resource recycling in out-of-order microprocessors. In Intl. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 2002

[PDF]
@inproceedings{m3:micro02,
  author = "Jos{\'e} F. Mart{\'\i}nez and Jose Renau and Michael C. Huang and Milos Prvulovic and Josep Torrellas",
  title = "Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors",
  booktitle = "International Symposium on Microarchitecture (MICRO)",
  address = "Istanbul, Turkey",
  month = nov,
  year = "2002" }
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